module check_edge (

    input   wire            clk,
    
    input   wire            wave,
    
    output  wire            flag_pos,
    output  wire            flag_neg   
);

    reg             [1:0]   reg_wave;
    reg                     reg_check;
    
    always @ (posedge clk) reg_wave <= {reg_wave[0], wave};
  
    always @ (posedge clk) reg_check <= reg_wave[1];
    
    assign flag_pos = reg_wave[1] & (~reg_check);
    assign flag_neg = reg_check & (~reg_wave[1]);
    
endmodule 




